(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to form a buried stack capacitor structure for a one transistor, random access memory (1T RAM), cell.
(2) Description of Prior Art
SRAM cells have in the past been fabricated using six transistors, usually comprised of four N channel, metal oxide semiconductor field effect transistor (MOSFET), devices, and of two P channel MOSFET devices. However to reduce processing costs the semiconductor industry has been attempting to fabricate smaller chips, with the smaller semiconductor chips still however offering device densities equal to, or greater than counterpart larger semiconductor chips. The attainment of a larger number of smaller semiconductor chips on a specific size starting substrate allow the processing cost of a specific chip to be reduced. However the use of smaller chips for SRAM technology create problems when attempting to place six transistors on the smaller semiconductor chip Therefore SRAM designs have focused on one transistor, 1T SRAM cells, comprised with a single metal oxide semiconductor field effect transistor (MOSFET) device, and a capacitor structure. This configuration, featuring a single transistor and a single capacitor structure, provides the same function as the six transistor design, however requiring less space and thus fulfilling the objective of constructing smaller semiconductor chips.
This invention will describe a novel process sequence in which a 1T RAM cell is fabricated using a buried stacked capacitor structure. A buried stacked capacitor structure requires less space than counterpart trench type, or stacked type capacitor structures. In addition the buried stack capacitor structure featured in this invention includes novel process features such as definition of a ring shaped storage node opening via a self-aligned etching procedure, as well as featuring the use of a combination of isotropic wet etch procedures, allowing a highly doped, implanted region to be formed at the interface of the storage node structure and semiconductor substrate, thus reducing the series resistance between these elements Prior art such as Selcuk, in U.S. Pat. No. 6,130,470, describe a process for forming buried sidewall capacitors between storage nodes, for a SRAM cell, however that prior art does not describe the novel process features highlighted in this present invention directed at fabrication of a buried stack capacitor structure as an component of a 1T RAM cell.
It is an object of this invention to fabricate a one transistor, static random access memory (1T RAM), cell, featuring a single MOSFET device and a buried stacked capacitor structure.
It is another object of this invention to define a self-aligned opening for the storage node structure of the buried stacked capacitor structure as part of the shallow trench isolation (STI) fabrication process, via a self-align etching procedure.
It is still another object of this invention to use isotropic etch procedures to laterally etch insulator layers, exposing regions of a semiconductor substrate and allowing a heavily doped region to be formed in these exposed regions, which when overlaid with a subsequent storage node structure, result in reduced node to substrate series resistance.
In accordance with the present invention a method of fabricating a buried stack capacitor structure for a 1T RAM cell is described. After formation of a silicon oxide filled, STI region in a composite insulator layer comprised of a silicon nitride layer and an underlying pad silicon oxide layer, and in a top portion of a semiconductor substrate, a silicon oxide cap layer is deposited. Photolithographic, (featuring a photoresist shape with an opening larger in diameter than the diameter of the STI region), and selective dry etching procedures, are used for self-aligned removal of a top portion of the silicon oxide in the STI region, with the selective dry etch procedure terminating at the appearance of the silicon nitride layer located overlying the top surface of the semiconductor substrate, adjacent to the perimeter of the STI region. In addition part of the photoresist shape is also used to protect a center portion of the STI region from the dry etch procedure, resulting in an STI shape comprised of an unetched, thick region of silicon oxide located in the center of the STI region, surrounded by the thinner, partially etched, silicon oxide. Lateral, isotropic etching of the cap, and pad silicon oxide layer exposing a portion of silicon nitride, followed by removal of the exposed silicon nitride portion, exposes a region of the semiconductor substrate adjacent to the edge of the STI region- A heavily doped region is then formed in exposed regions, such as the exposed region of semiconductor substrate located adjacent to the edge of the ST region, as well as in the sides of the same semiconductor substrate, exposed in the thinned STI region. Deposition of a polysilicon layer, followed by a chemical mechanical polishing (CXP) procedure, results in a storage node structure comprised with horizontal features located on the bottom surfaces of the partially etched STI region, as well as on the top surface of the heavily doped region in semiconductor substrate, and comprised of attaching vertical features located on the heavily doped sides of the semiconductor substrate, exposed in the partially etched STI region. Subsequent processing features formation of a capacitor dielectric layer on the polysilicon storage node structure, followed by formation of a capacitor top plate structure, resulting in a ring shaped, buried stacked capacitor structure for a 1T RAM cell, in which the substrate to node series resistance is minimized via use of the heavily doped region formed in a region encompassing the interface of the semiconductor substrate and the side of the partially etched STI region.